Turbo codes have attracted great attention in the industry and research communities since their introduction in 1993 because of their remarkable performance. Turbo codes operate near (with SNR gap of 0.7 dB or less) the ultimate limits of capacity of a communication channel set by Claude E. Shannon (Shannon C. E., “A Mathematical Theory of Communication”, Bell Systems Tech. Journal, 27, pp. 379-423, July 1948). Turbo codes were first proposed in “Near Shannon Limit Error-Correcting Coding: Turbo Codes”, Proc IEEE Int. Conf. Commun., Geneva, Switzerland, pp. 1064-1070, 1993, by Berrou, Galvieux and Thitimajshims. Turbo codes are constructed using two concatenated constituent convolutional coders. In the turbo coding scheme, two component codes on different interleaved versions of the same information sequence are generated. On the decoder side, two maximum a posteriori (MAP) decoders are used to decode the decisions in an iterative manner. The MAP decoding algorithm uses the received data and parity symbols (which correspond to parity bits computed from actual and interleaved versions of data bits) and other decoder soft output (extrinsic) information to produce more reliable decisions. Both of these references are hereby incorporated in this application by reference in their entirety.
The MAP decoder is used to determine the most likely information bit that has been transmitted. To do so, the MAP decoder calculates the posteriori probabilities value for each transmitted data bit. Then the bit is decoded by assigning a decision value that corresponds to the maximum posteriori probability calculated by the Log Likelihood Ratio (LLR). Turbo codes have better performance as the number of iterations and the interleaver size increases in the channel environment. However, as the number of iterations and the interleaver size are increased, it requires more computational power which translates to more MIPS (million instructions per second) if done using a programmable core like a Digital Signal Processor (DSP) or more power if done in a hardware block.
For more information see U.S. Pat. No. 7,346,833 B2 and the references cited therein and the extensive list of references identified in the Background of Invention of that patent, all of which are hereby incorporated in this application by reference in their entireties.